Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents Instantiating Intellectual Property with the IP Catalog and Parameter Editor

Many Intel FPGA IP cores include a resource and timing estimation netlist that the Synplify software uses to report more accurate resource utilization and timing performance estimates, and uses timing-driven optimization rather than a black box function.

To create this netlist file, perform the following steps:

  1. Select the IP core in the IP Catalog.
  2. Click Next to open the Parameter Editor.
  3. Click Set Up Simulation, which sets up all the EDA options.
  4. Turn on the Generate netlist option to generate a netlist for resource and timing estimation and click OK.
  5. Click Generate to generate the netlist file.

The Intel® Quartus® Prime software generates a file <output file>_syn.v. This netlist contains the gray box information for resource and timing estimation, but does not contain the actual implementation. Include this netlist file in your Synplify project. Next, include the IP core variation wrapper file <output file>.v|vhd in the Intel® Quartus® Prime project along with your Synplify .vqm output netlist.

If your IP core does not include a resource and timing estimation netlist, the Synplify software must treat the IP core as a black box.