Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents Inferring ROM

When a ROM block is inferred from an HDL design, the Synplify software uses an Intel FPGA IP core to target the device memory architecture. For some devices, the Synplify software maps directly to memory block device atoms instead of instantiating an IP core in the .vqm file.

Follow these guidelines for the Synplify software to successfully infer ROM in a design:

  • The address line must be at least two bits wide.
  • The ROM must be at least half full.
  • A CASE or IF statement must make 16 or more assignments using constant values of the same width.