- 2.8.2. Running the Intel® Quartus® Prime Software Manually Using the Precision Synthesis‑Generated Tcl Script
- 18.104.22.168. Creating a Single Intel® Quartus® Prime Project for a Standard Incremental Compilation Flow
22.214.171.124. Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores
You might want to change this behavior to reduce run times in the Synplify software, because generating the netlist files can take several minutes for large designs, or if the Synplify software cannot access your Intel® Quartus® Prime software installation to generate the files. Changing this behavior might speed up the compilation time in the Synplify software, but the Quality of Results (QoR) might be reduced.
The Synplify software directs the Intel® Quartus® Prime software to generate information in two ways:
- Some IP cores provide a “clear box” model—the Synplify software fully synthesizes this model and includes the device architecture-specific primitives in the output .vqm netlist file.
- Other IP cores provide a “gray box” model—the Synplify software reads the resource information, but the netlist does not contain all the logic functionality.
Note: You need to turn on Generate netlist when using the gray box model. For more information, see the Intel® Quartus® Prime online help.
For these IP cores, the Synplify software uses the logic information for resource and timing estimation and optimization, and then instantiates the IP core in the output .vqm netlist file so the Intel® Quartus® Prime software can implement the appropriate device primitives. By default, the Synplify software uses the clear box model when available, and otherwise uses the gray box model.
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