Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

1.10.2. Including Files for Intel® Quartus® Prime Placement and Routing Only

In the Synplify software, you can add files to your project that are used only during placement and routing in the Intel® Quartus® Prime software. This can be useful if you have gray or black boxes for Synplify synthesis that require the full design files to be compiled in the Intel® Quartus® Prime software.

You can also set the option in a script using the -job_owner par option.

The example shows how to define files for a Synplify project that includes a top-level design file, a gray box netlist file, an IP wrapper file, and an encrypted IP file. With these files, the Synplify software writes an empty instantiation of “core” in the .vqm file and uses the gray box netlist for resource and timing estimation. The files core.v and core_enc8b10b.v are not compiled by the Synplify software, but are copied into the place-and-route directory. The Intel® Quartus® Prime software compiles these files to implement the “core” IP block.

Commands to Define Files for a Synplify Project

add_file -verilog -job_owner par "core_enc8b10b.v"
add_file -verilog -job_owner par "core.v"
add_file -verilog "core_gb.v"
add_file -verilog "top.v"

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