Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Public
Document Table of Contents

2.6. Mapping the Precision Synthesis Design

In the next steps, you set constraints and map the design to technology‑specific cells. The Precision Synthesis software maps the design by default to the fastest possible implementation that meets your timing constraints. To accomplish this, you must specify timing requirements for the automatically determined clock sources. With this information, the Precision Synthesis software performs static timing analysis to determine the location of the critical timing paths. The Precision Synthesis software achieves the best results for your design when you set as many realistic constraints as possible. Be sure to set constraints for timing, mapping, false paths, multicycle paths, and other factors that control the structure of the implemented design.

Mentor Graphics recommends creating an .sdc file and adding this file to the Constraint Files section of the Project Files list. You can create this file with a text editor, by issuing command-line constraint parameters, or by directing the Precision Synthesis software to generate the file automatically the first time you synthesize your design. By default, the Precision Synthesis software saves all timing constraints and attributes in two files: precision_rtl.sdc and precision_tech.sdc. The precision_rtl.sdc file contains constraints set on the RTL-level database (post-compilation) and the precision_tech.sdc file contains constraints set on the gate-level database (post- synthesis) located in the current implementation directory.

You can also enter constraints at the command line. After adding constraints at the command line, update the .sdc file with the update constraint file command. You can add constraints that change infrequently directly to the HDL source files with HDL attributes or pragmas.

Note: The Precision .sdc file contains all the constraints for the Precision Synthesis project. For the Intel® Quartus® Prime software, placement constraints are written in a .tcl file and timing constraints for the Timing Analyzer are written in the Intel® Quartus® Prime .sdc file.

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