Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents set_max_delay and set_min_delay

The maximum delay and minimum delay for a point-to-point timing path constraint is specified in the Precision Synthesis software.

Using the set_max_delay Constraint

set_max_delay -from {<from_node_list>} -to {<to_node_list>} <delay_value>

Using the set_min_delay Constraint

set_min_delay -from {<from_node_list>} -to {<to_node_list>} <delay_value>

The set_max_delay and set_min_delay commands specify that the maximum and minimum respectively, required delay for any start point in <from_node_list> to any endpoint in <to_node_list> must be less than or greater than <delay_value>. Typically, you use these commands to override the default setup constraint for any path with a specific maximum or minimum time value for the path.

The node lists can contain a collection of clocks, registers, ports, pins, or cells. The -from and -to parameters specify the source (start point) and the destination (endpoint) of the timing path, respectively. The source list (<from_node_list>) cannot include output ports, and the destination list (<to_node_list>) cannot include input ports. If you include more than one node on a list, you must enclose the nodes in quotes or in braces ({ }).

If you specify a clock in the source list, you must specify a clock in the destination list. Applying set_max_delay or set_min_delay setting between clocks applies the exception from all registers or ports driven by the source clock to all registers or ports driven by the destination clock. Applying exceptions between clocks is more efficient than applying them for specific node-to-node, or node-to-clock paths. If you want to specify pin names in the list, the source must be a clock pin and the destination must be any non-clock input pin to a register. Assignments from clock pins, or to and from cells, apply to all registers in the cell or for those driven by the clock pin.