2.9.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor
To create this netlist file, perform the following steps:
- Select the IP function in the IP Catalog.
- Click Next to open the Parameter Editor.
- Click Set Up Simulation, which sets up all the EDA options.
- Turn on the Generate netlist option to generate a netlist for resource and timing estimation and click OK.
- Click Generate to generate the netlist file.
The Intel® Quartus® Prime software generates a file <output file>_syn.v. This netlist contains the “gray box” information for resource and timing estimation, but does not contain the actual implementation. Include this netlist file into your Precision Synthesis project as an input file. Then include the IP core wrapper file <output file>.v|vhd in the Intel® Quartus® Prime project along with your EDIF or VQM output netlist.
The generated “gray box” netlist file, <output file>_syn.v , is always in Verilog HDL format, even if you select VHDL as the output file format.