Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis
ID
683796
Date
9/24/2018
Public
1.1. About Synplify Support
1.2. Design Flow
1.3. Hardware Description Language Support
1.4. Intel Device Family Support
1.5. Tool Setup
1.6. Synplify Software Generated Files
1.7. Design Constraints Support
1.8. Simulation and Formal Verification
1.9. Synplify Optimization Strategies
1.10. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features
1.11. Incremental Compilation and Block-Based Design
1.12. Synopsys Synplify* Support Revision History
1.10.1.1. Instantiating Intel FPGA IP Cores with IP Catalog Generated Verilog HDL Files
1.10.1.2. Instantiating Intel FPGA IP Cores with IP Catalog Generated VHDL Files
1.10.1.3. Changing Synplify’s Default Behavior for Instantiated Intel FPGA IP Cores
1.10.1.4. Instantiating Intellectual Property with the IP Catalog and Parameter Editor
1.10.1.5. Instantiating Black Box IP Cores with Generated Verilog HDL Files
1.10.1.6. Instantiating Black Box IP Cores with Generated VHDL Files
1.10.1.7. Other Synplify Software Attributes for Creating Black Boxes
1.11.1. Design Flow for Incremental Compilation
1.11.2. Creating a Design with Separate Netlist Files for Incremental Compilation
1.11.3. Using MultiPoint Synthesis with Incremental Compilation
1.11.4. Creating Multiple .vqm Files for a Incremental Compilation Flow With Separate Synplify Projects
1.11.5. Performing Incremental Compilation in the Intel® Quartus® Prime Software
2.1. About Precision RTL Synthesis Support
2.2. Design Flow
2.3. Intel Device Family Support
2.4. Precision Synthesis Generated Files
2.5. Creating and Compiling a Project in the Precision Synthesis Software
2.6. Mapping the Precision Synthesis Design
2.7. Synthesizing the Design and Evaluating the Results
2.8. Exporting Designs to the Intel® Quartus® Prime Software Using NativeLink Integration
2.9. Guidelines for Intel FPGA IP Cores and Architecture-Specific Features
2.10. Incremental Compilation and Block-Based Design
2.11. Mentor Graphics Precision* Synthesis Support Revision History
2.8.1. Running the Intel® Quartus® Prime Software from within the Precision Synthesis Software
2.8.2. Running the Intel® Quartus® Prime Software Manually Using the Precision Synthesis‑Generated Tcl Script
2.8.3. Using the Intel® Quartus® Prime Software to Run the Precision Synthesis Software
2.8.4. Passing Constraints to the Intel® Quartus® Prime Software
2.9.1. Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files
2.9.2. Instantiating IP Cores With IP Catalog-Generated VHDL Files
2.9.3. Instantiating Intellectual Property With the IP Catalog and Parameter Editor
2.9.4. Instantiating Black Box IP Functions With Generated Verilog HDL Files
2.9.5. Instantiating Black Box IP Functions With Generated VHDL Files
2.9.6. Inferring Intel FPGA IP Cores from HDL Code
2.10.1. Creating a Design with Precision RTL Plus Incremental Synthesis
2.10.2. Creating Multiple Mapped Netlist Files With Separate Precision Projects or Implementations
2.10.3. Creating Black Boxes to Create Netlists
2.10.4. Creating Intel® Quartus® Prime Projects for Multiple Netlist Files
2.10.5. Hierarchy and Design Considerations
1.11.4.1. Manually Creating Multiple .vqm Files With Black Boxes
To create multiple .vqm files manually in the Synplify software, create a separate project for each lower-level module and top-level design that you want to maintain as a separate .vqm file for an incremental compilation partition. Implement black box instantiations of lower-level partitions in your top-level project.
Figure 6. Partitions in a Hierarchical Design
The partition top contains the top-level block in the design (block A) and the logic that is not defined as part of another partition. In this example, the partition for top-level block A also includes the logic in one of its sub-blocks, block C. Because block F is contained in its own partition, it is not treated as part of the top‑level partition A. Another separate partition, partition B, contains the logic in blocks B, D, and E. In a team-based design, engineers can work independently on the logic in different partitions. One netlist is created for the top-level module A and its submodule C, another netlist is created for module B and its submodules D and E, while a third netlist is created for module F.