Intel® Quartus® Prime Standard Edition User Guide: Third-party Synthesis

ID 683796
Date 9/24/2018
Document Table of Contents Creating Multiple Intel® Quartus® Prime Projects for a Bottom-Up Incremental Compilation Flow

Use the .tcl file that is created for each .vqm file by the Synplify software for each Synplify project. This method generates multiple Intel® Quartus® Prime projects, one for each block in the design. The designers in the project can optimize their own blocks separately within the Intel® Quartus® Prime software and export the placement of their own blocks.

Designers should create a LogicLock region to create a design floorplan for each block to avoid conflicts between partitions. The top-level designer then imports all the blocks and assignments into the top-level project. This method allows each block in the design to be optimized separately and then imported into one top-level project.

Figure 8. Design Flow Using Multiple Synplify Projects and Multiple Intel® Quartus® Prime Projects