Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents Synchronizer

The synchronizer is a 1 bit wide and 6 bit deep FIFO buffer that compensates for the phase difference between DPA_diffioclk—the optimal clock that the DPA block selects—and the LVDS_diffioclk that the fractional PLLs produce. The synchronizer can only compensate for phase differences, not frequency differences, between the data and the receiver’s input reference clock.

An optional port, RX_FIFO_RESET, is available to the internal logic to reset the synchronizer. The synchronizer is automatically reset when the DPA first locks to the incoming data. Altera recommends using RX_FIFO_RESET to reset the synchronizer when the data checker indicates that the received data is corrupted.

Note: The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.