Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

6.6. High-Speed Differential I/O Interfaces and DPA in Stratix® V Devices Revision History

Date Version Changes
December 2017 2017.12.15
  • Added a note to Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only topic to clarify that spread-spectrum input clock is not supported in LVDS.
  • Updated for latest Intel branding standards.
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12
  • Changed figure title "Corner PLLs Driving DPA-enabled Differential I/Os" to "Invalid Usage of Corner PLLs Driving DPA-enabled Differential I/Os".
  • Added LVDS and DPA Clock Network figure in Guideline: Using DPA-Enabled Differential Channels.
  • Updated all figures in Guideline: Using DPA-Enabled Differential Channels.
  • Updated guidelines for using both corner PLLs in Stratix V Devices.
  • Updated figures in Guideline: Using DPA-Disabled LVDS Differential Channels.
January 2015 2015.01.23
  • Removed statement on explanation related to rx_synclock for figure "LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode)".
  • Updated figure LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode) and figure Receiver Datapath in Soft-CDR Mode.
  • Added a note to leave rx_enable and rx_inclock to be unconnected for figure LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode).
  • Updated timing diagram for Phase Relationship for External PLL Interface Signals to reflect the correct phase shift and frequency for outclk2.
January 2014 2014.01.10
  • Updated the statement about setting the phase of the clock in relation to data in the topic about transmitter clocking.
  • Updated the figure that shows the phase relationship for the external PLL interface signals.
  • Clarified that "one row of separation" between two groups of DPA-enabled channels means a separation of one differential channel.
  • Clarified that "internal PLL option" refers to the option in the ALTLVDS megafunction.
  • Updated the topic about emulated LVDS buffers to clarify that you can use unutilized true LVDS input channels (instead "buffers") as emulated LVDS output buffers.
June 2013 2013.06.21

Updated the figure about data realignment timing to correct the data pattern after a bit slip.

May 2013 2013.05.06
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Added link to the known document issues in the Knowledge Base.
  • Removed all references to column and row I/Os. Stratix V devices have I/O banks on the top and bottom only.
  • Changed the color of the transceiver blocks in the high-speed differential I/O location diagram for clarity.
  • Updated the pin placement guidelines section to add figures and new topic about using DPA-disabled differential channels.
  • Added a topic about emulated LVDS buffers.
  • Edited the topic about true LVDS buffers.
  • Added a topic that lists the SERDES I/O standards support and the respective Quartus II assignment values.
  • Corrected the outclk2 waveform in Figure 114 to show -18° phase shift (as labeled).
  • Clarified that the programmable VOD assignment value of "0" is also applicable for mini-LVDS.
  • Updated the data realignment timing figure to improve clarity.
  • Updated the receiver data realignment rollover figure to improve clarity.
December 2012 2012.12.28
  • Reorganized content and updated template.
  • Added Altera_PLL settings for external PLL usage in DPA and non-DPA modes.
  • Moved the PLL and clocking section into design guideline topics.
  • Updated external PLL clocking examples without DPA and soft-CDR. Altera_PLL now supports entering negative phase shift.
  • Added external PLL clocking example and settings for DPA and soft-CDR mode.
  • Updated the LVDS channel tables to list the number of channels per side for each device package instead of just for the largest package.
  • Removed the “LVDS Direct Loopback Mode” section.
June 2012 1.4
  • Added Table 6–2.
  • Updated Table 6–1, Table 6–3, Table 6–4, and Table 6–5.
  • Updated Figure 6–21.
  • Updated “Non-DPA Mode”, “Soft-CDR Mode”, and “PLLs and Stratix V Clocking” sections.
November 2011 1.3
  • Updated Table 6–2.
  • Updated Example 6–1.
  • Updated “LVDS Direct Loopback Mode” and “LVDS Interface with the Use External PLL Option Enabled” sections.
May 2011 1.2
  • Chapter moved to volume 2 for the 11.0 release.
  • Added Table 6–2 and Table 6–3.
  • Updated Table 6–1.
  • Updated Figure 6–2 and Figure 6–23.
  • Updated “Locations of the I/O Banks”, “Programmable Pre-Emphasis”, “Differential Receiver”, “Fractional PLLs and Stratix V Clocking”, and “DPA-Enabled Channels, DPA-Disabled Channels, and Single-Ended I/Os” sections.
  • Minor text edits.
December 2010 1.1

No changes to the content of this chapter for the Quartus II software 10.1.

July 2010 1.0 Initial release.