Stratix V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 11/23/2021
Document Table of Contents

11.6. Power-Up Sequence

The Stratix® V devices require a power-up sequence as shown in the following figure to prevent excessive inrush current and ensure proper transceiver functionality. This power-up sequence is divided into four power groups. Group 1 contains the first power rails to ramp. The VCC , VCCHIP , and VCCHSSI power rails in this group must ramp to a minimum of 80% of their full rail before any other power rails may start. Group 1 power rails can continue to ramp to full rail. The power rails in Group 2 and Group 4 can start to ramp in any order after Group 1 has reached its minimum 80% threshold. When the last power rail in Group 2 reaches 80% of its full rail, the remaining power rails in Group 3 may start their ramp. During this time, Group 2 power rails may continue to ramp to full rail. Power rails in Group 3 may ramp in any order. All power rails must ramp monotonically. The complete power-up sequence must meet either the standard or fast POR delay time, depending on the POR delay setting that is used.

Figure 203. Power-Up Sequence Requirement for Stratix® V DevicesPower up VCCBAT at any time. If VCC , VCCR_GXB , and VCCT_GXB have the same voltage level, they can be powered by the same regulator in Group 1 and ramp simultaneously.

Stratix® V devices may power down all power rails simultaneously. However, all rails must reach 0 V within 100 ms from the start of power-down.

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