Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents LVDS Compensation Mode

The purpose of LVDS compensation mode is to maintain the same data and clock timing relationship seen at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted (180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock network, including the difference in delay between the following two paths:

  • Data pin-to-SERDES capture register
  • Clock input pin-to-SERDES capture register

The output counter must provide the 180° phase shift.

Figure 75. Example of Phase Relationship Between the Clock and Data in LVDS Compensation Mode