8.7.1. DATA Clock (DCLK)
Stratix® V devices generate the serial clock, DCLK, that provides timing to the serial interface. In the AS configuration scheme, Stratix® V devices drive control signals on the falling edge of DCLK and latch the configuration data on the following falling edge of this clock pin.
The maximum DCLK frequency supported by the AS configuration scheme is 100 MHz except for the AS multi-device configuration scheme. You can source DCLK using CLKUSR or the internal oscillator. If you use the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options dialog box, in the Configuration page of the Intel® Quartus® Prime software.
After power-up, DCLK is driven by a 12.5 MHz internal oscillator by default. The Stratix® V device determines the clock source and frequency to use by reading the option bit in the programming file.
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