Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

5.7.8. OCT Calibration in User Mode

In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER signals are used to calibrate and serially transfer calibration codes from each OCT calibration block to any I/O.

Table 47.  OCT Calibration Block Ports for User ControlThis table lists the user-controlled calibration block signal names and their descriptions
Signal Name Description
OCTUSRCLK Clock for OCT block.
ENAOCT Enable OCT Calibration (generated by user IP).
  • ENOCT is 0—each signal enables the OCT serializer for the corresponding OCT calibration block.
  • ENAOCT is 1—each signal enables OCT calibration for the corresponding OCT calibration block.
S2PENA_bank# Serial-to-parallel load enable per I/O bank.
nCLRUSR Clear user.
Figure 99. Signals Used for User Mode CalibrationThis figure shows the flow of the user signal.

When ENAOCT is 1, all OCT calibration blocks are in calibration mode. When ENAOCT is 0, all OCT calibration blocks are in serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.

Note: You must generate all user signals on the rising edge of the OCTUSRCLK signal.
Figure 100. OCT User Mode Signal—Timing Waveform for One OCT BlockThis figure shows the user mode signal-timing waveforms.

OCT Calibration

To calibrate OCT block N (where N is a calibration block number), you must assert ENAOCT one cycle before asserting ENASERN . You must also set nCLRUSR low for one OCTUSRCLK cycle before the ENASERN signal is asserted. Assert the ENASERN signals for 1,000 OCTUSRCLK cycles to perform RS OCT and RT OCT calibration. You can deassert ENAOCT one clock cycle after the last ENASER is deasserted.

Serial Data Transfer

After you complete calibration, you must serially shift out the 32 bit OCT calibration codes (16 bit RS OCT and 16 bit RT OCT) from each OCT calibration block to the corresponding I/O buffers. Only one OCT calibration block can send out the codes at any time by asserting only one ENASERN signal at a time. After you deassert ENAOCT, wait at least one OCTUSRCLK cycle to enable any ENASERN signal to begin serial transfer. To shift the 32 bit code from the OCT calibration block N, you must assert ENASERN for exactly 32 OCTUSRCLK cycles. Between two consecutive asserted ENASER signals, there must be at least one OCTUSRCLK cycle gap, as shown in the preceding figure.

After calibrated codes are shifted in serially to each I/O bank, the calibrated codes must be converted from serial to parallel format before being used in the I/O buffers. The preceding figure shows the S2PENA signals that can be asserted at any time to update the calibration codes in each I/O bank. All I/O banks that received the codes from the same OCT calibration block can have S2PENA asserted at the same time, or at a different time, even while another OCT calibration block is calibrating and serially shifting codes. The S2PENA signal is asserted one OCTUSRCLK cycle after ENASER is deasserted for at least 25 ns. You cannot use I/Os for transmitting or receiving data when their S2PENA is asserted for parallel codes transfer.