Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Public
Document Table of Contents
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7.3. External Memory Interface Features in Stratix V Devices

The Stratix® V I/O elements (IOE) provide built-in functionality required for a rapid and robust implementation of external memory interfacing.

The following device features are available for external memory interfaces:

  • DQS phase-shift circuitry
  • PHY Clock (PHYCLK) networks
  • DQS logic block
  • Dynamic on-chip termination (OCT) control
  • IOE registers
  • Delay chains
  • Delay-locked loops (DLLs)
  • Read- and write-leveling support
  • Trace mismatch compensation
  • Read FIFO blocks
  • Slew rate adjustment
  • Programmable drive strength