Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents
Give Feedback

1.1.4. LAB Control Signals

Each LAB contains dedicated logic for driving the control signals to its ALMs, and has two unique clock sources and three clock enable signals.

The LAB control block generates up to three clocks using the two clock sources and three clock enable signals. An inverted clock source is considered as an individual clock source. Each clock and the clock enable signals are linked.

De-asserting the clock enable signal turns off the corresponding LAB-wide clock.

The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. The MultiTrack interconnect’s inherent low skew allows clock and control signal distribution in addition to data. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity.

Clear and Preset Logic Control

LAB-wide signals control the logic for the register’s clear signal. The ALM directly supports an asynchronous clear function. You can achieve the register preset through the NOT-gate push-back logic option in the Intel® Quartus® Prime software. Each LAB supports up to two clears.

Stratix® V devices provide a device-wide reset pin (DEV_CLRn) that resets all the registers in the device. An option set before compilation in the Intel® Quartus® Prime software controls this pin. This device-wide reset overrides all other control signals.

Figure 5. LAB-Wide Control Signals for Stratix V DevicesThis figure shows the clock sources and clock enable signals in a LAB.