Stratix V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 11/23/2021
Document Table of Contents

4.3. Clock Networks and PLLs in Stratix V Devices Revision History

Document Version Changes
  • Updated PLL Locations in Stratix® V Devices section with fractional PLL information.
  • Corrected the signal name from clkswitch to extswitch.
  • Updated the description for the automatic switchover with manual override mode in the Clock Switchover section.
  • Updated the description about the extswitch signal in the Manual Clock Switchover section.
Date Version Changes
December 2016 2016.12.09 Added a note to dedicated refclk pin in Fractional PLL High-Level Block Diagram.
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
January 2014 2014.01.10
  • Removed Preliminary tags for clock resources, clock input pin connections to GCLK and RCLK networks, and PLL features tables.
  • Updated information on dual-regional clock region.
  • Added label for PLL strip in PLL locations diagrams.
  • Added descriptions for PLLs located in a strip.
  • Updated VCO post-scale counter, K, to VCO post divider.
  • Added information on PLL cascading.
  • Added information on programmable phase shift.
  • Updated automatic clock switchover mode requirement.
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base.
  • Updated PCLK clock sources per device quadrant.
  • Added PCLK networks resources and diagram for Stratix® V E devices.
  • Updated PCLK clock sources in hierarchical clock networks in each spine clock per quadrant diagram.
  • Added PCLK networks in clock network sources section.
  • Updated dedicated clock input pins in clock network sources section.
  • Added information on C output counters for PLLs.
  • Added power down mode in PLL features table.
  • Added information on PLL physical counters.
  • Updated the PLL locations index from CEN_X<#>_Y<#>, COR_X<#>_Y<#>, and LR_X<#>_Y<#> to FRACTIONALPLL_X<#>_Y<#>.
  • Removed LVPECL I/O standard support for clock output pin pairs.
  • Updated PLL support for EFB mode.
  • Updated the scaling factors for PLL output ports.
  • Updated the fractional value for PLL in fractional mode.
  • Moved all links to the Related Information section of respective topics for easy reference.
  • Reorganized content.
December 2012 2012.12.28
  • Added note to indicate that the figures shown are the top view of the silicon die.
  • Added diagram for PLL physical counter orientation.
  • Updated PLL locations diagrams.
  • Removed information on pfdena PLL control signal.
  • Removed information on PLL Compensation assignment in the Quartus II software.
  • Updated the fractional value for PLL in fractional mode.
  • Reorganized content and updated template.
June 2012 1.4
  • Added Table 4–5 and Table 4–6.
  • Added Figure 4–6, Figure 4–8, Figure 4–20, Figure 4–22, and Figure 4–33.
  • Updated Table 4–1, Table 4–2, and Table 4–3.
  • Updated Figure 4–3, Figure 4–5, Figure 4–17, Figure 4–18, Figure 4–19, and Figure 4–21.
  • Added “PLL Migration Guidelines”, “Implementing Multiple PLLs in Normal Mode and Source Synchronous Mode”, “Clock Switchover”, and “PLL Reconfiguration and Dynamic Phase Shift” sections.
  • Updated “Clock Networks in Stratix V Devices”, “Clock Network Sources”, and “Clock Multiplication and Division” sections.
November 2011 1.3 Updated Figure 4–19 and Figure 4–28.
May 2011 1.2
  • Chapter moved to volume 2 for the 11.0 release.
  • Updated Table 4–1.
  • Updated Figure 4–3, Figure 4–4, Figure 4–5, Figure 4–6, Figure 4–15, Figure 4–17, Figure 4–18, Figure 4–20, Figure 4–25, and Figure 4–28.
  • Updated “Zero-Delay Buffer Mode” and “External Feedback Mode” sections.
  • Added “PLL Clock Outputs” section.
December 2010 1.1 No changes to the content of this chapter for the Quartus II software 10.1.
July 2010 1.0 Initial release.

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