Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

11.7. Power-On Reset Circuitry

The POR circuitry keeps the Stratix® V device in the reset state until the power supply outputs are within the recommended operating range.

A POR event occurs when you power up the Stratix® V device until the power supplies reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the Stratix® V device I/O pins and programming registers remain tri-stated, during which device configuration could fail.

Figure 204. Relationship Between tRAMP and POR Delay

The Stratix® V POR circuitry uses an individual detecting circuitry to monitor each of the configuration-related power supplies independently. The main POR circuitry is gated by the outputs of all the individual detectors. The main POR signal is asserted when the power starts to ramp up. This signal is released after the last ramp-up power reaches the POR trip level during power up.

In user mode, the main POR signal is asserted when any of the monitored power goes below its POR trip level. Asserting the POR signal forces the device into the reset state.

The POR circuitry checks the functionality of the I/O level shifters powered by the VCCPD and VCCPGM power supplies during power-up mode. The main POR circuitry waits for all the individual POR circuitries to release the POR signal before allowing the control block to start programming the device.

Figure 205. Simplified POR Diagram for Stratix V Devices