Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

5. I/O Features in Stratix V Devices

This chapter provides details about the features of the Stratix® V I/O elements (IOEs) and how the IOEs work in compliance with current and emerging I/O standards and requirements.

The Stratix® V I/Os support the following features:

  • True LVDS channels in all I/O banks support SGMII, SPI-4.2, and XSBI applications
  • Hard dynamic phase alignment (DPA) and serializer/deserializer (SERDES) support in I/O banks on all sides of the device with DPA
  • Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
  • Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, and SSTL I/O standards across all I/O banks
  • Double data rate (DDR), single data rate (SDR), and half data rate input and output options
  • Serializer/deserializer (SERDES)
  • Deskew, read and write leveling, and clock-domain crossing functionality for high-performance memory interface
  • Programmable output current strength
  • Programmable slew rate
  • Programmable bus-hold
  • Programmable pull-up resistor
  • Programmable pre-emphasis
  • Programmable I/O delay
  • Programmable voltage output differential (VOD)
  • Open-drain output
  • On-chip series termination (RS OCT) with and without calibration
  • On-chip parallel termination (RT OCT)
  • On-chip differential termination (RD OCT)
Note: The information in this chapter is applicable to all Stratix® V variants, unless noted otherwise.