Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents
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1.1.5. ALM Resources

Each ALM contains a variety of LUT-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and four registers.

With up to eight inputs for the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function with up to six inputs and certain seven-input functions.

One ALM contains four programmable registers. Each register has the following ports:

  • Data
  • Clock
  • Synchronous and asynchronous clear
  • Synchronous load

Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control signals of an ALM register.

GPIO pins or internal logic drives the clock enable signal.

For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM.

Note: The Intel® Quartus® Prime software automatically configures the ALMs for optimized performance.
Figure 6. ALM High-Level Block Diagram for Stratix V Devices