Stratix V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 11/23/2021
Document Table of Contents

7.3.2. External Memory Interface Datapath

The following figure shows an overview of the memory interface datapath that uses the Stratix® V I/O elements. In the figure, the DQ/DQS read and write signals may be bidirectional or unidirectional, depending on the memory standard. If the signal is bidirectional, it is active during read and write operations. You can bypass each register block.

Figure 145. External Memory Interface Datapath Overview for Stratix V Devices

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