Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents Fractional PLL Usage

You can configure the fractional PLL to function either in the integer or in the enhanced fractional mode. One fractional PLL can use up to 18 output counters and all external clock outputs. Two adjacent fractional PLLs share the 18 output counters.

Fractional PLLs can be used as follows:

  • Reduce the number of required oscillators on the board
  • Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source
  • Compensate clock network delay
  • Zero delay buffering
  • Transmit clocking for transceivers