Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

4. Clock Networks and PLLs in Stratix V Devices

This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs) in Stratix® V devices. The Intel® Quartus® Prime software enables the PLLs and their features without external devices.