Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

11.2. Programmable Power Technology

Stratix® V devices offer the ability to configure portions of the core, called tiles, for high-speed or low-power mode of operation performed by the Intel® Quartus® Prime software without user intervention. Setting a tile to high-speed or low-power mode is accomplished with on-chip circuitry and does not require extra power supplies brought into the Stratix® V device. In a design compilation, the Intel® Quartus® Prime software determines whether a tile should be in high-speed or low-power mode based on the timing constraints of the design.

Stratix® V tiles consist of the following:

  • Memory logic array block (MLAB)/ logic array block (LAB) pairs with routing to the pair
  • MLAB/LAB pairs with routing to the pair and to adjacent digital signal processing (DSP)/ memory block routing
  • TriMatrix memory blocks
  • DSP blocks
  • PCI Express® (PCIe®) hard IP
  • Physical coding sublayer (PCS)

All blocks and routing associated with the tile share the same setting of either high-speed or low-power mode. By default, tiles that include DSP blocks or memory blocks are set to high-speed mode for optimum performance. Unused DSP blocks and memory blocks are set to low-power mode to minimize static power. Clock networks do not support programmable power technology.

With programmable power technology, faster speed grade FPGAs may require less power because there are fewer high-speed MLAB and LAB pairs, when compared with slower speed grade FPGAs. The slower speed grade device may have to use more high-speed MLAB and LAB pairs to meet performance requirements.

The Intel® Quartus® Prime software sets unused device resources in the design to low-power mode to reduce the static power. It also sets the following resources to low-power mode when they are not used in the design:

  • LABs and MLABs
  • TriMatrix memory blocks
  • DSP blocks

If a phase-locked loop (PLL) is instantiated in the design, you may assert the areset pin high to keep the PLL in low-power mode.

Altera recommends that you power down unused PCIe HIPs, per side, by connecting the PCIe HIP power to GND on the PCB for additional power savings. All of the HIPs on a side of the device must be unused to be powered down. For additional information refer to the pin connection guidelines.

Table 102.  Programmable Power Capabilities for Stratix® V DevicesThis table lists the available Stratix® V programmable power capabilities. Speed grade considerations can add to the permutations to give you flexibility in designing your system.
Feature Programmable Power Technology
Routing Yes
Memory Blocks Fixed setting 30
DSP Blocks Fixed setting30
Clock Networks No
30 Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By default, unused DSP blocks and memory blocks are set to low-power mode.