Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents LVPECL Termination

The Stratix® V devices support the LVPECL I/O standard on input clock pins only:

  • LVPECL input operation is supported using LVDS input buffers.
  • LVPECL output operation is not supported.
Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL input common-mode voltage.
Note: Altera recommends that you use IBIS models to verify your LVPECL AC/DC-coupled termination.
Figure 109. LVPECL AC-Coupled TerminationThe 50 Ω resistors used at the receiver end are external to the device.

Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the Stratix® V LVPECL input buffer specification.

Figure 110. LVPECL DC-Coupled Termination