Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

5.1.3. MultiVolt I/O Interface in Stratix® V Devices

The MultiVolt I/O interface feature allows Stratix® V devices in all packages to interface with systems of different supply voltages.

You can connect the VCCIO pins to a 1.2, 1.25, 1.35, 1.5, 1.8, 2.5, or 3.0 V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply. For example, when VCCIO pins are connected to a 1.5 V power supply, the output levels are compatible with 1.5 V systems.

For LVDS applications:

  • The LVDS I/O standard is not supported when VCCIO is 3.0 V.
  • The LVDS input operations are supported when VCCIO is 1.2, 1.25, 1.35, 1.5, 1.8, or 2.5 V.
  • The LVDS output operations are only supported when VCCIO is 2.5 V.
Table 30.  MultiVolt I/O Support in Stratix® V Devices
VCCIO (V) VCCPD (V) 6 Input Signal (V) Output Signal (V)
1.2 2.5 1.2 1.2
1.25 2.5 1.25 1.25
1.35 2.5 1.35 1.35
1.5 2.5 1.5, 1.8 1.5
1.8 2.5 1.5, 1.8 1.8
2.5 2.5 2.5, 3.0, 3.3 2.5
3.0 3.0 2.5, 3.0, 3.3 3.0, 3.3

The pin current may be slightly higher than the default value. Verify that the VOL maximum and VOH minimum voltages of the driving device do not violate the applicable VIL maximum and VIH minimum voltage specifications of the Stratix® V device.

The VCCPD power pins must be connected to a 2.5 V or 3.0 V power supply. Using these power pins to supply the pre-driver power to the output buffers increases the performance of the output pins.

Note: If the input signal is 3.0 V or 3.3 V, Altera recommends that you use an external clamping diode on the I/O pins.
6 Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL, HSUL, and Differential HSUL are powered by VCCPD