Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

9.5.2. Error Detection Frequency

You can control the speed of the error detection process by setting the division factor of the clock frequency in the Intel® Quartus® Prime software. The divisor is 2n, where n can be any value listed in the following table.

The speed of the error detection process for each data frame is determined by the following equation:

Figure 191. Error Detection Frequency Equation
Table 90.  Error Detection Frequency Range for Stratix V DevicesThe following table lists the frequencies and valid values of n.
Internal Oscillator Frequency Error Detection Frequency n Divisor Range
Maximum Minimum
100 MHz 100 MHz 390 kHz 0, 1, 2, 3, 4, 5, 6, 7, 8 1 – 256