22.214.171.124. DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input DQS/CQ and CQn signals to be shifted by the amount specified by the DQS phase-shift circuitry or the logic array.
There are four delay elements in the DQS delay chain that have the same characteristics:
- Delay elements in the DQS logic block
- Delay elements in the DLL
The first delay chain closest to the DQS/CQ pin is shifted either by the DQS delay settings or by the sum of the DQS delay setting and the phase-offset setting. The DQS delay settings can come from the DQS phase-shift circuitry on either end of the I/O banks or from the logic array.
The number of delay chains required is transparent because the UniPHY IP automatically sets it when you choose the operating frequency.
In Stratix® V devices, if you do not use the DLL to control the DQS delay chains, you can input your own gray-coded 7 bit settings using the delayctrlin[6..0] signals available in the UniPHY IP. These settings control 1, 2, 3, or all 4 delay elements in the DQS delay chains. The UniPHY IP core can also dynamically choose the number of DQS delay chains required for the system. The amount of delay is equal to the sum of the intrinsic delay of the delay element and the product of the number of delay steps and the value of the delay steps. You can also bypass the DQS delay chain to achieve a 0° phase shift.
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