Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents Source Synchronous Mode

If the data and clock arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard.

Altera recommends source synchronous mode for source synchronous data transfers.

Figure 74. Example of Phase Relationship Between Clock and Data in Source Synchronous Mode

The source synchronous mode compensates for the delay of the clock network used and any difference in the delay between the following two paths:

  • Data pin to the IOE register input
  • Clock input pin to the PLL phase frequency detector (PFD) input

The Stratix® V PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode.