Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

1.3. LAB Power Management Techniques

The following techniques are used to manage static and dynamic power consumption within the LAB:

  • To save AC power, the Intel® Quartus® Prime software forces all adder inputs low when the ALM adders are not in use.
  • Stratix® V LABs operate in high-performance mode or low-power mode. The Intel® Quartus® Prime software automatically chooses the appropriate mode for the LAB, based on your design and to optimize speed versus leakage trade-offs.
  • Clocks represent a significant portion of dynamic power consumption because of their high switching activity and long paths. The LAB clock that distributes a clock signal to registers within a LAB is a significant contributor to overall clock power consumption. Each LAB’s clock and clock enable signals are linked. For example, a combinational ALUT or register in a particular LAB using the labclk1 signal also uses the labclkena1 signal. To disable a LAB-wide clock power consumption without disabling the entire clock tree, use the LAB-wide clock enable to gate the LAB-wide clock. The Intel® Quartus® Prime software automatically promotes register-level clock enable signals to the LAB-level. All registers within the LAB that share a common clock and clock enable are controlled by a shared, gated clock. To take advantage of these clock enables, use a clock-enable construct in your HDL code for the registered logic.