Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Public
Document Table of Contents

4.1.2.3. Periphery Clock Networks

Depending on the routing direction, Stratix® V devices provide vertical PCLKs from the top and bottom periphery, and horizontal PCLKs from the left and right periphery.

Clock outputs from the dynamic phase aligner (DPA) block, programmable logic device (PLD)-transceiver interface clocks, I/O pins, and internal logic can drive the PCLK networks.

PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Stratix® V device.

Figure 51. PCLK Networks for Stratix® V GS D5 Device, and Stratix® V GX A3 (with 36 transceivers) and A4 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Figure 52. PCLK Networks for Stratix® V GX B5 and B6 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Figure 53. PCLK Networks for Stratix® V GT C5 and C7 Devices, and Stratix® V GX A5 and A7 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Figure 54. PCLK Networks for Stratix® V GS D3 and D4 Devices, and Stratix® V GX A3 (with 24 transceivers) Device This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Figure 55. PCLK Networks for Stratix® V GS D6 and D8 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Figure 56. PCLK Networks for Stratix® V E E9 and EB Devices, and Stratix® V GX A9, AB, BB, and B9 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.