Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

1.4. Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices Revision History

Date Version Changes
December 2016 2016.12.09 Added description on clock source in the LAB Control Signals section.
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
January 2014 2014.01.10 Added multiplexers for the bypass paths and register outputs in the following diagrams:
  • ALM High-Level Block Diagram for Stratix® V Devices
  • Input Function in Normal Mode
  • Template for Supported 7-Input Functions in Extended LUT Mode for Stratix® V Devices
  • ALM in Arithmetic Mode for Stratix® V Devices
  • ALM in Shared Arithmetic Mode for Stratix® V Devices
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base.
  • Updated the available LABs to use as a MLAB.
  • Removed register chain outputs information in ALM output section.
  • Moved all links to the Related Information section of respective topics for easy reference.
December 2012 2012.12.28 Reorganized content and updated template.
June 2012 1.4
  • Updated Figure 1–5, Figure 1–6, and Figure 1–12.
  • Removed register chain expression.
  • Minor text edits.
November 2011 1.3
  • Updated Figure 1–1, Figure 1–4, and Figure 1–6.
  • Removed “Register Chain” section.
May 2011 1.2
  • Chapter moved to volume 2 for the 11.0 release.
  • Updated Figure 1–6.
  • Minor text edits.
December 2010 1.1 No changes to the content of this chapter for the Quartus II software 10.1.
July 2010 1.0 Initial release.