Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

7.2. Memory Interface Pin Support in Stratix V Devices

In the Stratix® V devices, the memory interface circuitry is available in every I/O bank that does not support transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations.

Stratix V devices also provide an independent DQS logic block for each CQn pin for complementary read-data strobe and clock operations

The memory clock pins are generated with double data rate input/output (DDRIO) registers.