Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

4.2. Stratix V PLLs

PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Stratix® V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs. The output counters in Stratix® V devices are dedicated to each fractional PLL that support integer or fractional frequency synthesis.

Two adjacent PLLs share 18 C output counters. Any number of C counters can be assigned to each PLL, as long as the total number used by the two PLLs is 18 or less.

The Stratix® V devices offer up to 32 fractional PLLs in the larger densities. All Stratix® V fractional PLLs have the same core analog structure and features support.

Table 25.  PLL Features in Stratix V Devices
Feature Support
Integer PLL Yes
Fractional PLL Yes
C output counters 18
M, N, C counter sizes 1 to 512
Dedicated external clock outputs 4 single-ended or 2 single-ended and 1 differential
Dedicated clock input pins 4 single-ended or 4 differential
External feedback input pin Single-ended or differential
Spread-spectrum input clock tracking Yes 2
Source synchronous compensation Yes
Direct compensation Yes
Normal compensation Yes
Zero-delay buffer compensation Yes
External feedback compensation Yes
LVDS compensation Yes
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes
Phase shift resolution 78.125 ps 3
Programmable duty cycle Yes
Power down mode Yes
2 Provided input clock jitter is within input jitter tolerance specifications.
3 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Stratix® V device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.