Stratix® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 10/18/2023
Document Table of Contents

8.1. Enhanced Configuration and Configuration via Protocol

Table 75.  Configuration Schemes and Features of Stratix® V Devices Stratix® V devices support 1.8 V, 2.5 V, and 3.0 V programming voltages and several configuration schemes.
Mode Data Width Max Clock Rate (MHz) Max Data Rate (Mbps) Decompression Design Security Partial Reconfiguration 14 Remote System Update
AS through the EPCS and EPCQ serial configuration device 1 bit, 4 bits 100 Yes Yes Yes
PS through CPLD or external microcontroller 1 bit 125 125 Yes Yes
FPP 8 bits 125 Yes Yes Parallel flash loader
16 bits 125 Yes Yes Yes15
32 bits 100 Yes Yes
CvP (PCIe) x1, x2, x4, and x8 lanes Yes Yes Yes
JTAG 1 bit 33 33

Instead of using an external flash or ROM, you can configure the Stratix® V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Stratix® V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

14 Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Altera for support.
15 Supported at a maximum clock rate of 62.5 MHz.