Stratix V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683665
Date 11/23/2021
Document Table of Contents

6.2.1. PLLs and Clocking for Stratix® V Devices

To generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks (diffioclk), the Stratix® V devices provide fractional PLLs in the high-speed differential I/O receiver and transmitter channels.

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