CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022

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5.14. TX_CTRL Register

Table 68.  TX_CTRL Register at Offset 0x34 Frequency differences between the control and status interface clock cpu_clk and the main CPRI Intel® FPGA IP clock cpri_clkout might cause non-zero read latency and more than one clock cycle of write latency when accessing this register.
Bits Field Name Type Value on Reset Description
31:0 tx_ctrl_data RW 32'b0 CPRI control word 32-bit section to be transmitted in CPRI hyperframe position Z.x, where x is the index in the tx_ctrl_x field of the CTRL_INDEX register. The tx_ctrl_seq field of the CTRL_INDEX register indicates whether this is the first, second, third, fourth, or fifth such 32-bit section.