CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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3.9. Real-Time Vendor Specific Interface

If you turn on Enable direct real-time vendor specific interface in the CPRI parameter editor, the real-time vendor specific interface is available. This interface allows direct access to the Real Time Vendor Specific words in the CPRI hyperframe. Check the rtvs_rx_valid and rtvs_tx_ready signals to ensure you read and write this interface at the time that corresponds to the correct position in the CPRI frame. If you implement the AUX interface, you can read the value on the aux_rx_seq or aux_tx_seq output signal to identify the current position in the frame.

This option is only available if you specify a CPRI line bit rate of 10.1376 Gbps for your IP core.

This interface is Avalon-ST compliant with a ready latency value of 1.

You can alter the transmit write latency with the Auxiliary and direct interfaces write latency cycle(s) parameter.

Table 28.  Real-Time Vendor Specific Interface Signals

All interface signals are clocked by the cpri_clkout clock. The Data path width parameter determines the interface type and width, where N= 32 or 64, C= 0 or 1, and D= 31 or 63.

Real-Time Vendor Specific RX Interface

Signal Name

Direction

Description

rtvsN_rx_valid[C:0] Output Each asserted bit indicates the corresponding 32-bit data on the current rtvs_rx_data bus is a valid real-time vendor-specific bytes.
rtvsN_rx_data[D:0] Output Real-time vendor-specific word received from the CPRI frame.
Real-Time Vendor Specific TX Interface

Signal Name

Direction

Description

rtvsN_tx_ready[C:0] Output Each asserted bit indicates corresponding 32-bit real-time vendor specific bytes on rtvs_tx_data is ready to be read on the next clock cycle
rtvsN_tx_valid[C:0] Input Write valid for rtvs_tx_data. Assertion of each bit indicates corresponding 32-bit data of rtvs_tx_data holds a valid value in the current clock cycle.
rtvsN_tx_data[D:0] Input Real-time vendor-specific word to be written to the CPRI frame. The IP core writes the current value of the rtvs_tx_data bus to the CPRI frame based on the rtvs_tx_ready signal from the previous cycle, and the rtvs_tx_valid signal in the current cycle.
Figure 41. Direct RTVS RX Timing DiagramDirect RTVS RX interface behavior in a CPRI IP running at 10.1376 Gbps, 32-bit interface.

The aux_rx_x and aux_rx_seq signals are not part of this interface and are available only if you turn on the AUX interface in your CPRI IP core variation. However, their presence in the timing diagram explains the timing of the rtvs_rx_valid output signal that you use to identify the clock cycles with valid RTVS data.



Figure 42. Direct RTVS TX Timing DiagramExpected behavior on the direct RTVS TX interface of a CPRI IP core running at 10.1376 Gbps, 32-bit interface.

The aux_tx_x and aux_tx_seq signals are not part of this interface and are available only if you turn on the AUX interface in your CPRI IP core variation. However, their presence in the timing diagram explains the timing of the rtvs_tx_ready output signal that you use to identify the clock cycles when you can write RTVS data to the CPRI frame.

Note that the write latency is one cpri_clkout clock cycle in this example.



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