CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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5.31. DELAY_CAL_RTD Register

Table 85.  DELAY_CAL_RTD Register at Offset 0x80 This register is available only in CPRI master Intel® FPGA IP cores with the single-trip delay calibration feature.
Bits Field Name Type Value on Reset Description
31:30 Reserved UR0 2'b0
29:28 cal_rtd_status RW 2'b0 Round trip delay calibration status. Valid values are:
  • 00: Calibration is turned off.
  • 01: Calibration is running.
  • 11: Error: Intel® FPGA IP core is unable to meet the calibration requirement.
  • 10: Calibration has completed or is in the monitoring stage.
27 Reserved UR0 1'b0
26:24 cal_rtd_ctrl RW 3'b0 Round trip delay calibration control. Valid values are one-hot:
  • Bit [26]: Active high reset bit that resets the calibration block. Use this bit to reset the calibration block after an error or to re-enable the calibration block to take it out of bypass mode.
  • Bit [25]: Enable or disable calibration block bypass mode. When the value of this bit is 1, round trip delay calibration is in bypass mode. When the value of this bit is 0, round trip delay calibration is not in bypass mode.
  • Bit [24]: Enable or disable round trip delay calibration. When the value of this bit is 1, round trip delay calibration is turned on. When the value of this bit is 0, round trip delay calibration is turned off.
23:20 Reserved UR0 4'b0
19:0 cal_rtd_usr RW 20'b0 Desired round-trip delay value.

Refer to the round_trip_delay register to identify current round trip delay value. Based on the round trip delay value, you can write any value to this register that is within the range of 0 to value in round_trip_delay. Unit is cpri_clkout cycles.

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