CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022

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3.15.1. CPU Interface Signals

Table 34.   CPRI Intel® FPGA IP Core CPU Interface SignalsThe CPRI IP core CPU interface has the following features:
  • Avalon-MM slave interface compliant.
  • Provides support for single cycle read and write operations: you can read or write a single register in a single access operation.
  • Supports a single cpu_clk clock cycle read latency and a zero cpu_clk clock cycle write latency for most registers.

Signal Name



cpu_clk Input Clocks the signals on the CPRI CPU interface. Supports any frequency that the device fabric supports.
cpu_reset_n Input Active low reset signal. Resets the CPRI CPU interface and all of the registers to which it provides access.

You should hold this signal asserted for one full cpu_clk cycle to ensure it is captured by the IP core.



Address for reads and writes. All CPRI control and status registers are 32 bits wide. By default, this address is a word address (addresses a 4-byte (32-bit) word), not a byte address. However, if you set Avalon-MM interface addressing type to Byte in the CPRI parameter editor, this address is a byte address.

cpu_byteenable[3:0] Input Data-byte enable signal


You must assert this signal to request a read transfer



You must assert this signal to request a write transfer



Write data



Read data



Indicates that the control and status interface is busy executing an operation. When the Intel® FPGA IP core deasserts this signal, the operation is complete and the read data is valid.



Interrupt request. All interrupts that you enable in the relevant register fields, assert this interrupt signal when they are triggered. You must check the relevant register fields to determine the cause or causes of the interrupt assertion.

Figure 52. Read Transaction on CPU Interface
Figure 53. Write Transaction on CPU Interface

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