CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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2.5.4. Adding the Off-Chip Clean-Up PLL

If your CPRI Intel® FPGA IP core is an RE slave, you must connect it to an off-chip clean-up PLL to clean up any jitter that occurs in the CDR output clock, before sending it to the reference clock input of the external TX PLL.

The clean-up PLL performs the clock synchronization necessary to address the CPRI v7.0 Specification requirements R-17, R-18, and R-18A, which address jitter and frequency accuracy in the RE core clock for radio transmission.

Drive the clean-up PLL with the CPRI IP core xcvr_recovered_clk output clock, and connect the cleaned up output to the external TX PLL input reference clock port. In the hybrid clocking mode, in 8110.08, 10137.6, 12165.12 and 24330.24 Mbps IP core variations, you should connect the cleaned up output to the cpri_coreclk input clock port as well. In the external clocking mode, you can optionally connect the cleaned up output to the cpri_coreclk input clock port.

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