CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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3.7. Ctrl_AxC Interface

If you turn on Enable direct ctrl_axc access interface in the CPRI parameter editor, the Ctrl_AxC interface is available. This interface allows direct access to the Ctrl_AxC subchannels in the CPRI frame, which are subchannels 4, 5, 6, and 7 in each hyperframe.

This interface is Avalon-ST compliant with a ready latency value of 1.

You can alter the transmit latency with the Auxiliary and direct interfaces write latency cycle(s) parameter.

Table 26.  Ctrl_AxC Interface SignalsAll interface signals are clocked by the cpri_clkout clock. The Data path width parameter determines the interface type and width, where N= 32 or 64, C= 3 or 7, and D= 31 or 63.
Ctrl_AxC RX Interface

Signal Name

Direction

Description

ctrlN_axc_rx_valid[C:0] Output Each asserted bit indicates the corresponding byte on the current ctrl_axc_rx_data bus is valid Ctrl_Axc data.
ctrlN_axc_rx_data[D:0] Output Ctrl_Axc data received from the CPRI frame. The ctrl_axc_rx_valid signal indicates which bytes are valid Ctrl_Axc data bytes.
Ctrl_AxC TX Interface

Signal Name

Direction

Description

ctrlN_axc_tx_ready[C:0] Output Each asserted bit indicates the IP core is ready to read Ctrl_Axc data from the corresponding byte of ctrl_axc_tx_data on the next clock cycle.
ctrlN_axc_tx_valid[C:0] Input Write valid for ctrl_axc_tx_data. Assert bit [n] to indicate that the corresponding byte on the current ctrl_axc_tx_data bus is valid Ctrl_Axc data.
ctrl_axc_tx_data[D:0] Input Ctrl_Axc data to be written to the CPRI frame. The IP core writes the individual bytes of the current value on the ctrl_axc_tx_data bus to the CPRI frame based on the ctrl_axc_tx_ready signal from the previous cycle, and the ctrl_axc_tx_valid signal in the current cycle.
Figure 37. Ctrl_Axc RX Interface Timing DiagramCtrl_Axc RX interface behavior in a CPRI IP running at 0.6144 Gbps.


The aux_rx_x and aux_rx_seq signals are not part of this interface and are available only if you turn on the AUX interface in your CPRI IP variation. However, their presence in the timing diagram explains the timing of the ctrl_axc_rx_valid output signal that you use to identify the clock cycles with valid Ctrl_Axc data.

Figure 38. Ctrl_Axc TX Interface Timing DiagramExpected behavior on the Ctrl_Axc TX interface of a CPRI IP core running at 0.6144 Gbps.

The aux_tx_x and aux_tx_seq signals are not part of this interface and are available only if you turn on the AUX interface in your CPRI IP variation. However, their presence in the timing diagram explains the timing of the ctrl_axc_tx_ready output signal that you use to identify the clock cycles when you can write Ctrl_Axc data to the CPRI frame. Note that the write latency is two cpri_clkout clock cycles in this example.



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