CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
Public

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1.2.1. Device Family Support

Table 1.   Intel® FPGA IP Core Device Support Levels

Device Support Level

Definition

Advance

The IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/O standards tradeoffs).

Preliminary

Intel has verified the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final

Intel has verified the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 2.   CPRI Intel® FPGA IP Core Device Family SupportShows the level of support offered by the CPRI IP core for each Intel® FPGA device family at time of publication. Refer to the latest timing models of the target device to determine the current level of support offered.

Device Family

Support

Intel® Agilex™ (F-tile) Preliminary
Intel® Agilex™ (E-tile) Final
Intel® Stratix® 10 (E-tile) Final
Intel® Stratix® 10 (L-tile and H-tile) Final

Intel® Arria® 10

Final
Arria V (GX and GT) Final

Arria V GZ

Final
Cyclone V (GX and GT) Final

Stratix V (GX and GT)

Final

Other device families

No support

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