CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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3.17.3. Extended Delay Measurement Interface

Table 38.  Extended Delay Measurement Interface Signals

Signal Name

Direction

Description

ex_delay_clk Input Clock for extended delay measurement.
ex_delay_reset_n Input Resets the extended delay measurement block. This signal is active low.

This reset signal is associated with the ex_delay_clk clock.

latency_sclk Input Clock for extended delay measurement of Intel® Stratix® 10 hard FIFOs.

You can (but need not) drive this clock at the same frequency as ex_delay_clk.

latency_sreset_n Input Resets the extended delay measurement soft logic for the Intel® Stratix® 10 hard FIFOs. This signal is active low.

This reset signal is associated with the latency_sclk clock.

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