CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs

The CPRI Intel® FPGA IP uses a dedicated clock, latency_sclk, to measure the delay through the RX and TX Intel® Stratix® 10 device hard FIFOs that are configured in the CPRI IP core.

The delay calculation process is identical for the two directions of flow through the IP core; the XCVR_TX_FIFO_DELAY and XCVR_RX_FIFO_DELAY registers hold the same information for the two directions.

To measure the current Tx delay through the hard FIFOs:

  • Check the tx_pcs_fifo_delay_valid and tx_core_fifo_delay_valid fields of the XCVR_TX_FIFO_DELAY register at offset 0x84 to ensure the delay count values are updated.
  • Add the delay count values in the tx_pcs_fifo_delay and tx_core_fifo_delay fields of the XCVR_TX_FIFO_DELAY register at offset 0x84.
  • Multiply the result by the clock period of the latency_sclk.
  • Divide this result by 128.

To measure the current Rx delay through the hard FIFOs:

  • Check the rx_pcs_fifo_delay_valid and rx_core_fifo_delay_valid fields of the XCVR_RX_FIFO_DELAY register at offset 0x88 to ensure the delay count values are updated.
  • Add the delay count values in the rx_pcs_fifo_delay and rx_core_fifo_delay fields of the XCVR_RX_FIFO_DELAY register at offset 0x88.
  • Multiply the result by the clock period of the latency_sclk.
  • Divide this result by 128.
Figure 55. Additional Delay Through Intel Stratix 10 Hard FIFOs

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