CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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3.3. CPRI Intel® FPGA IP Core Reset Requirements

To reset the entire CPRI IP core, you must assert the reset signals to the IP core and to the required external reset controller logic. The external reset controller logic resets only the transceiver. If you instantiate a duplex CPRI IP core, you must instantiate two PHY Reset Controllers to implement this logic, one for the TX data path and one for the RX data path. The two reset signals reset_tx_n and reset_rx_n each cause the reset logic to reset the relevant data path of the IP core. If you connect these two reset signals to the corresponding PHY Reset Controllers, each one also causes the transceiver in that data path to reset.

In the case of a duplex CPRI IP core , you can assert the reset_n signal instead of asserting the two reset signals reset_tx_n and reset_rx_n. However, unless you also connect the reset_n signal to the external reset controllers, the transceivers do not reset in this case.

In addition, some individual interfaces to the IP core have their own reset signals to reset only the associated interface and logic.

Table 22.   CPRI Intel® FPGA IP Core Input Reset SignalsYou can assert all reset signals asynchronously to any clock. However, you must hold each reset signal asserted for one full clock period of its associated clock, to ensure it is captured by the IP. Intel recommends using the transceiver PHY reset controller IP to drive the following signals:
CPRI Reset Signal Polarity Associated Clock Information
xcvr_tx_analogreset Active high Analog reset to transmitter from external reset controller.
xcvr_tx_digitalreset Active high Digital reset to transmitter from external reset controller.
xcvr_rx_analogreset Active high

Analog reset to receiver from external reset controller.

xcvr_rx_digitalreset Active high Digital reset to receiver from external reset controller.
reset_n Active low reconfig_clk Asynchronous global reset signal. Resets the IP core soft logic. This signal does not reset the CSR registers, the extended delay measurement settings, or the transceivers.

To reset the CSR registers, you must assert the cpu_reset_n signal. To reset the extended delay measurement settings, you must assert the ex_delay_reset_n signal.

To reset the transceiver you must drive the reset input port of the required PHY Reset Controllers.

ehip_rst_n Active low Asynchronous reset signal that resets the CPRI PHY TX/RX soft logic and the PCS. This signal connects to i_sl_tx_rst_n and i_sl_rx_rst_n of the CPRI PHY.

This reset signal is only present in the Intel® Stratix® 10 E-tile and Intel® Agilex™ E- tile device variations.

ehip_rst_csr_n Active low Asynchronous reset signal that resets the TX/RX soft logic and the PCS, subset of the PMA functions and PCS/PMA CSRs. This signal connects to i_sl_csr_rst_n of the CPRI PHY.
reset_tx_n Active low reconfig_clk Asynchronous global reset signal that resets the TX path of the CPRI IP core. Resets the IP core soft logic. To reset the transceiver you must drive the reset input port of the required PHY Reset Controller.
reset_rx_n Active low reconfig_clk Asynchronous global reset signal that resets the RX path of the CPRI IP core. Resets the IP core soft logic. To reset the transceiver you must drive the reset input port of the required PHY Reset Controller.
ex_delay_reset_n Active low ex_delay_clk Resets the extended delay measurement block.
latency_sreset_n Active low latency_sclk Resets the Intel® Stratix® 10 hard FIFO delay measurement soft logic.
reconfig_reset Active high reconfig_clk Asynchronous reset signal. Resets the CPRI Intel® Arria® 10 or Intel® Stratix® 10 or Intel® Agilex™ transceiver reconfiguration interface and all of the registers to which it provides access.

In IP cores that target a V-series (28-nm) device, this signal is involved in rate switching and auto-rate negotiation.

In Intel® Arria® 10, Intel® Stratix® 10 and Intel® Agilex™ variations, this signal is not present if you turn off all of Enable start-up sequence state machine, Enable Native PHY Debug Master Endpoint(NPDME), transceiver capability, control and status registers access, and parameters only available in Intel® Arria® 10 variations, Enable line bit rate auto-negotiation, Enable single-trip delay calibration.

In variations that target other devices, this signal is not present if you turn off all of Enable line bit rate auto-negotiation, Enable start-up sequence state machine.

cpu_reset_n Active low cpu_clk Resets the CPRI CPU interface and all of the registers to which it provides access.
mii_txreset_n Active low mii_txclk Resets the MII transmitter interface and FIFO write logic.
mii_rxreset_n Active low mii_rxclk Resets the MII receiver interface and FIFO read logic.
gmii_txreset_n Active low gmii_txclk Resets the GMII transmitter interface and FIFO write logic.
gmii_rxreset_n Active low gmii_rxclk Resets the GMII receiver interface and FIFO read logic.
Figure 22. Required External BlocksAn example showing how you could connect required components to a single CPRI Intel® FPGA IP core that target V-series, Intel® Arria® 10 and Intel® Stratix® 10 L- and H-tile devices.

To reset the CPRI IP core, you must assert the active low reset_tx_n, reset_rx_n, reset_tx_n and reset_rx_n, or reset_n signals, as appropriate.

To reset the transceiver, you must trigger the reset controller logic. If you make the optional connection to drive the reset_rx_n or reset_n port from the same source as the reset signal for the RX side Reset Controller, asserting the active low reset_rx_n or reset_n signal also triggers the reset controller logic. If you make the optional connection to drive the reset_tx_n or reset_n port from the same source as the reset signal for the TX side Reset Controller, asserting the active low reset_tx_n or reset_n signal also triggers the TX reset controller logic.

When you trigger the reset controllers, they should deassert the xcvr_reset_tx_ready and xcvr_reset_rx_ready input ready signals to the IP core. After each reset controller completes resetting the transceiver and IP core data path, it should assert the relevant ready signal.

For information about resetting the Intel® Stratix® 10 E- tile and Intel® Agilex™ E- tile transceiver, refer to the Resetting Transceiver Channels.

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