CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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3.4.1. Start-Up Sequence Interface Signals

After reset, if you turned on Enable start-up sequence state machine in the CPRI Intel® FPGA IP, the internal state machine performs link synchronization and other initialization tasks. If you did not turn on Enable start-up sequence state machine, user logic must perform these functions.

The signals visible in the interface depend on whether or not you turned on Enable start-up sequence state machine.

Table 23.  Start-Up Sequence Interface Signals

All interface signals are clocked by the cpri_clkout clock.

Signal Name

Direction

Description

state_startup_seq[2:0] Output Indicates the state of the CPRI start-up sequence state machine. This signal has the following valid values:
  • 3'b000: State A: Standby
  • 3'b001: State B: L1 Synchronization
  • 3'b011: State C: Protocol Setup
  • 3'b010: State D: Control and Management Setup
  • 3'b110: State E: Interface and VSS Negotiation
  • 3'b111: State F: Operation
  • 3'b101: State G: Passive Link

This signal is available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.

state_l1_synch[2:0] Output State B condition indicator. Indicates the state of the CPRI receiver L1 synchronization state machine. This signal has the following valid values:
  • 3'b000: XACQ1
  • 3'b001: XACQ2
  • 3'b011: XSYNC1
  • 3'b010: XSYNC2
  • 3'b110: HFNSYNC
nego_bitrate_complete Input Indicates the CPRI line bit rate negotiation is complete. Input from external CPRI line bit rate negotiation block.

If you do not turn on Enable line bit rate auto-negotiation in the CPRI parameter editor, you should tie this signal high.

This signal is available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.

Asserting this signal advances the start-up sequence state machine from state B to state C. The IP core writes the value of this signal to the nego_bitrate_complete field of the START_UP_SEQ register at offset 0x24.

nego_protocol_complete Input

Indicates the CPRI protocol version negotiation is complete.

This signal is available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.

Asserting this signal advances the start-up sequence state machine from state C to state D. The IP core writes the value of this signal to the nego_protocol_complete field of the START_UP_SEQ register at offset 0x24.

nego_cm_complete Input

Indicates the Control and Management negotiation is complete.

This signal is available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.

Asserting this signal advances the start-up sequence state machine from state D to state E. The IP core writes the value of this signal to the nego_cm_complete field of the START_UP_SEQ register at offset 0x24.

nego_vss_complete Input

Indicates the Vendor Specific negotiation is complete.

This signal is available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.

Asserting this signal advances the start-up sequence state machine from state E to state F. The IP core writes the value of this signal to the nego_vss_complete field of the START_UP_SEQ register at offset 0x24.

nego_l1_timer_expired Input If you do not turn on Enable protocol version and C&M channel setting auto-negotiation in the CPRI parameter editor, drive this signal from your user-defined L1 timer to indicate that the L1 timer has expired.

Note that if you do not turn on Enable protocol version and C&M channel setting auto-negotiation, user logic is expected to maintain an L1 timer outside the IP core.

This signal is available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.

If you also turn on Enable protocol version and C&M channel setting auto-negotiation in the CPRI parameter editor, you should tie this signal low so it does not interfere with the internal L1 timer.

Figure 24. Start-Up Sequence State Machine Timing Diagram


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