CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

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2.5.6. Transceiver PLL Calibration

Transceiver calibration is required for correct and optimal performance. You must calibrate the following Intel transceiver PLLs:
  • You must calibrate a TX transceiver PLL for Arria V and Stratix V designs.
  • You must calibrate ATX PLL, CMU PLL, fPLL for your Intel® Arria® 10, and Intel® Stratix® 10 L- and H- tile designs.
The power up calibration completes under the following conditions:
  • For Arria V and Stratix V designs: Dynamic Reconfiguration Controller reconfig_clk and ATX PLL REFCLK is present the correct frequency, and stable before the start of FPGA configuration.
  • For Intel® Arria® 10 designs: CLKUSR, CDR REFCLK, TX PLL REFCLK, are present, the correct frequency, and stable before the start of FPGA configuration.
  • For Intel® Stratix® 10 L- and H- tile designs: OSC_CLK_1, CDR_REFCLK, TX PLL REFCLK are present, the correct frequency, and stable before the start of FPGA configuration.
In some CPRI systems, the REFCLK may not be present, the correct frequency, or stable for some transceiver components before the start of FPGA configuration. For example an REC system, or a GPS sourced REFCLK. In this case, you must perform a User Mode Calibration when the clocks are present, the correct frequency, and stable. User Mode Calibration is also required after dynamic reconfiguration of the transceiver to another CPRI line rate.
You can perform the User Mode Calibration through the following interfaces:
  • User calibration of Arria V and Stratix V ATX PLL is done through the Dynamic Reconfiguration Controller IP interface.
  • User calibration of Intel® Arria® 10, and Intel® Stratix® 10 L- and H-tile devices is done through the transceiver PHY and TX PLL Avalon® Memory Mapped interfaces.
You can find the instruction for implementing the User Mode Calibration in the device specific PHY User Guides.

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