CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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2.5.7. Reference and System PLL Clock for your IP Design

Each F-tile system must instantiate one F-Tile Reference and System PLL Clocks Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel FPGA IP performs three main functions:
  1. Configure reference clock for FHT PMA:
    • Enable the FHT common PLLs and select the reference clock source for FHT common PLL
    • Specify the FHT reference clock source frequency
  2. Configure reference clock for FGT PMA:
    • Enable FGT reference clocks and specify the reference clock frequency
    • Specify FGT CDR output
  3. Configure system PLL:
    • Enable system PLL and specify its mode
    • Specify the reference clock source and frequency for system PLL
Note: In your IP design, you must include an F-Tile Reference and System PLL Clocks Intel FPGA IP core to pass logic generation flow.

The F-Tile Reference and System PLL Clocks Intel FPGA IP must always connect to a protocol based Intel FPGA IP. The F-Tile Reference and System PLL Clocks Intel FPGA IP cannot be compiled or simulated as a standalone IP. For more information on parameters and port list for F-Tile Reference and System PLL Clocks Intel FPGA IP core, refer to the F-tile Architecture and PMA/FEC Direct PHY IP User Guide.

When you design multiple interfaces or protocol-based IP cores within a single F-tile, you must use only one instance of the F-Tile Reference and System PLL Clocks Intel FPGA IP core to configure:
  • All required reference clocks for FGT PMA (up to 10) and FHT PMA (up to 2) to implement multiple interfaces within a single F-tile.
  • All required FHT common PLLs (up to 2) to implement multiple interfaces within a single F-tile.
  • All required System PLLs (up to 3) to implement multiple interfaces within a single F-tile.
  • All required reference clocks for system PLLs (up to 8 – shared with FGT PMA) to implement multiple interfaces within a single F-tile.

When you design multiple interfaces or protocol-based IP cores within a single F-tile, you can only use three System PLLs. For example, you can use one System PLL for PCIe and two for Ethernet and other protocols. However, there are other use cases where you can use all three for various interfaces within the Ethernet and PMA-Direct digital blocks. As there are only three System PLLs, multiple interfaces or protocol-based IP cores with different line rates may have to share a System PLL. While sharing a System PLL, the interface with the highest line rate determines the system PLL frequency, and the interfaces with the lower line rates must be overclocked. For more information, refer to the F-tile Architecture and PMA/FEC Direct PHY IP User Guide.

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